This invention relates to semiconductor memory devices and methods of manufacture thereof, and more particularly to an N-channel silicon gate MOS RAM cell.
Semiconductor memory cells of the one-transistor type are used in N-channel silicon gate MOS RAM's as described in U.S. Pat. No. 3,909,631, issued Sept. 30, 1975 to N. Kitagawa, and assigned to Texas Instruments Incorporated, and described in Electronics, Sept. 13, 1973, p. 116. The most widely manufactured device of this type contains 4096 or 2.sup.12 bits, referred to in the industry as a "4K RAM". The costs in the production of semiconductor devices are such that most of the expense is in bonding, packaging, testing, handling, and the like, rather than the cost of the small chip of silicon which contains the actual circuitry. Thus, any circuit which can be contained within a chip of a given size, for example, 30,000 square mils, will cost about the same as any other. By forming "16K" or 16384 (2.sup.14) memory cells or bits in a chip, large economies in the cost per bit can result if reasonable yields are obtained. As the size of a chip increases, the yield decreases, so that at sizes above about 180 mils on a side the advantages are outweighed by reduction in yield. Accordingly, it is desireable to reduce the area occupied by each bit or cell in a RAM.
One type of N-channel MOS one-transistor memory cell employing double-level polycrystalline silicon is described in my copending patent application Ser. No. 648,594, filed Jan 12, 1976, now abandoned, assigned to Texas InstrumentS. The present invention is an improvement on the cell of my previous application.
One-transistor cells in MOS integrated circuits employ storage capacitors of the type having a silicon oxide dielectric as set forth in U.S. Pat. No. 3,350,760, issued Nov. 7, 1967, to Jack s. Kilby, assigned to Texas Instruments. These may be of the so-called gated type, i.e. voltage dependent, and may have ion implanted regions thereunder as set forth in copending application Ser. No. 645,171 filed Dec. 29, 1975 (now abandoned) and Ser. No. 828,359, a continuation of Ser. No. 645,171. filed Aug. 29, 1977 (now U.S. Pat. No. 4,249,194) by Gerald D. Rogers, assigned to Texas Instruments Incorporated.
In a dynamic RAM using one-transistor cells, the reliability of the storage capacitor is most critical, since the capacitors constitute a major portion of the total thin oxide area of the chip. Generally, reliability and yield of a device are both inversely related to the area of the chip occupied by their oxide. The capacitor dielectric areas are more critical than the gate areas of the transistors because they are larger and are under a high potential stress at all times. Life test data on N-channel MOS dynamic RAM devices shows that 80 to 90% of reliability related failures are due to oxide defects in the storage capacitors. If the electric field intensity in the storage capacitor dielectric can be reduced, the reliability can be increased. Reliability of a thin silicon oxide dielectric in a capacitor is highly dependent on the electric field intensity in the oxide. Alternatively, by reducing the field intensity, the oxide can be made thinner so that the capacitance per unit area may be increased, allowing a reduction in all area thin oxide area.
The principal object of this invention is to provide an improved random access memory cell of higher reliability, smaller size, and/or higher yield. Another object is to provide an improved method of making N-channel silicon gate RAM devices.